Efeito do Multicasting na Coerência de Cache com Diretórios “Full Map” num Sistema Multiprocessador com Rede Crossbar
Resumo
No presente trabalho especifica-se e analisa-se um protocolo de coerência de cache baseado nos esquemas de diretório distribuído "full-map" para o "cluster" de um sistema multiprocessador com rede de interconexão crossbar com propriedade de "multicasting". A análise de desempenho considerada é baseada nas transmissões feitas através da rede (tráfego da rede), para três protocolos considerados (um protocolo "snoopy", esquema diretório com rede crossbar clássica, e a nossa proposta: esquema diretório com crossbar "multicasting") e estabelecem-se diferenças no seu desempenho.
Referências
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HERROD, S.A. Tango-Lite: A Multiprocessor Simulation Environment - Introduction and User's Guide. Technical Report, Stanford University, Sep. 1993.
GOLDSMCHMIDT, S.R. Simulation of Multiprocessors: Accuracy and Performance. PhD. Thesis, DEE, University of Stanford, Jun. 1993.
STENSTROM, P. A survey of Cache Coherence Schemes for Multiprocessors. IEEE Computer, v. 23, n. 6, p. 12-24, Jun. 1990.
CHO, K.; ADAMS,W.S. VLSI Implementation of a 256x256 Crossbar Interconnection Network. In: International Parallel Processing Symposium, IEEE. Proceedings 6th., p. 289-93, Mar. 1992.
TAMIR, Y.; CHI, H.C. Symmetric Crossbar Arbiters for VLSI Communications Switches. IEEE Transactions on Parallel and Distributed Systems, v. 4, n. 1, p. 13-27, Jan. 1993.
MOREIRA, J.E. Proposal for a High Performance Scalable Multiprocessor. University of Illinois at Urbana-Champaign, Mar. 1993.
LENOSKI, D.; LAUDON, J.; JOE, T.; NAKAHIRA, D.; STEVENS, L.; GUPTA, A. ; HENNESSY, J. The DASH Prototype: Logic Overhead and Performance. IEEE Transactions on Parallel and Distributed Systems, v. 4, n. 1, p. 41-61, Jan. 1993 .
D.LENOSKI, D.; LAUDON, J.; GHARACHORLOO, K.; WEBER, W; GUPTA, A.; HENNESY, J.; HOROWITZ, M.; LAM, M.S. The Standford DASH Multiprocessor. IEEE Computer,, p. 63-79, Mar. 1992.
PI596 Working Group, SCI (Scalable Coherence Interface) - Cache Coherence Overview. Technical Report Revision 0.33, IEEE Computer Society, Nov. 1989.
PAPAMARCOS, M.S;.PATEL, J.H. A Low-Overhead Coherence Solution for Multiprocessars with Private Cache Memories. In: Proceedings Ann. Symp. on Computer Architecture, IEEE, 11th, p. 348-54, 1984
ARCHIBALD, J; BAER, J.L. An Econornical Solution to the Cache Coherence Problem. In: Ann. Symp. on Computer Architecture, IEEE, 11th, Proceedings, p. 355-62, 1984.
GOODMAN, J.R. Using Cache Memory to Reduce Processar Memory Traffic. In: Ann. symp. on Computer Architecture, IEEE, Proceedings of 10th, p. 124-31, 1983.
HERROD, S.A. Tango-Lite: A Multiprocessor Simulation Environment - Introduction and User's Guide. Technical Report, Stanford University, Sep. 1993.
GOLDSMCHMIDT, S.R. Simulation of Multiprocessors: Accuracy and Performance. PhD. Thesis, DEE, University of Stanford, Jun. 1993.
Publicado
01/08/1994
Como Citar
ORDOÑEZ, Edward. D. M.; DELGADO, Martha X. T.; SANTOS, Celso A. S.; KOFUJI, Sergio T..
Efeito do Multicasting na Coerência de Cache com Diretórios “Full Map” num Sistema Multiprocessador com Rede Crossbar. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 6. , 1994, Caxambu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1994
.
p. 199-211.
DOI: https://doi.org/10.5753/sbac-pad.1994.21886.
