Estratégias para a Redução de Consumo de Energia e Aumento de Confiabilidade em IoT
Resumo
A Internet das Coisas (IoT) demanda novos desafios no projeto dos dispositivos computacionais e eletrônicos. Um destes desafios é a redução de consumo dos componentes desta grande rede de dispositivos conectados, sendo que a maioria permanece em conexão permanente. Outro aspecto importante, em um grande número de aplicações, especialmente em áreas críticas como saúde e transporte é a confiabilidade. Este artigo visa dar um panorama de estratégias de projeto que temos desenvolvido para a redução de consumo e aumento de confiabilidade de circuitos componentes da IoT, tais como redução do número de transistores nos dispositivos, aplicando técnicas de otimização, novas arquiteturas e projeto físico tolerante a efeitos de radiação.
Referências
AGUIAR, Y., ZIMPECK, A., MEINHARDT, C., REIS, R. (2016), “Permanent and Single Event Transient Faults Reliability Evaluation EDA Tool”, Microelectronics Reliability, Volume 64, September 2016, Pages 63-67, published by Elsevier B.V., 2016. ISSN: 0026-2714.
ANANTECH (2014), [link]
CONCEIÇÃO, C., MOURA, G., PISONI, F., REIS, R. (2017), “A Cell Clustering Technique to Reduce Transistor Count”, 24th IEEE International Conference on Electronics, Circuits and Systems – ICECS2017, Batumi, Georgia, December 5 - 8, 2017, p. 186-189, DOI: 10.1109/ICECS.2017.8291996
GENNARO, R., ROSA, F., OLIVEIRA, A., KASTENSMIDT, F., OST, L., REIS, R. (2017), “Analyzing the Impact of Fault Tolerance Methods in ARM Processors under Soft Errors Running Linux and Parallelization APIs”, IEEE Transactions on Nuclear Science, Volume: 64, Issue: 8, August 2017, ISSN: 1558-1578, DOI: 10.1109/TNS.2017.2706519
LAZZARI, C., WIRTH, G., KASTENSMIDT, F., ANGHEL, L., REIS, R. (2011), “Asymmetric Transistor Sizing Targeting Radiation-Hardened Circuits”, Journal on Electrical Engineering, Springer, DOI: 10.1007/s00202-011-0212-8, June 2011.
KASTENSMIDT, F., CARRO, L.; REIS, R. (2006), “Fault-Tolerance Techniques for SRAM-Based FPGA”, Springer. April 2006, 183 p., ISBN 0-387-31068-1
NEUBERGER, G., WIRTH, G., REIS, R., (2014) “Protecting Chips Against Hold Time Violations Due to Variability”, Springer, 107 p., 2014. ISBN 978-94-007-2426-6. DOI: 10.1007/978-94-007-2427-3
NICOLAIDIS, M. (1999), “Time redundancy based soft-error tolerance to rescue nanometer technologies”. In: IEEE VLSI TEST SYMPOSIUM, 17., 1999. Proceedings... IEEE Computer Society, 1999. p. 86-94.
POSSER, G., FLACH, G., WILKE, G., REIS, R. (2011), “Gate Sizing Minimizing Delay and Area”, ISVLSI2011. IEEE Computer Society Annual Symposium on VLSI, Chennai, India, July 4-6, 2011. p. 315-316, ISBN 978-0-7695-4447-2. DOI: 10.1109/ISVLSI.2011.92
REIMANN, T., SZE, C., REIS, R. (2016), “Challenges of Cell Selection Algorithms in Industrial High Performance Microprocessor Designs”, Integration, Elsevier B. V., Volume 52, January 2016, Pages 347-354, ISSN: 0167-9260, DOI: 10.1016/j.vlsi.2015.09.001
REIS, R., (2010) “Redução de Consumo pela Otimização de Componentes”, SEMISH 2010, Anais do 37º Seminário Integrado de Software e Hardware, Belo Horizonte, 21 a 22 de julho de 2010, p. 371-379, ISSN: 2175-2761.
REIS, R. (2011A), “Design Automation of Transistor Networks, a New Challenge”. IEEE International Symposium on Circuits and Systems, ISCAS2011, Rio de Janeiro, Brasil, May 15-19, 2011. IEEE Press. p. 2485-2488, ISBN: 978-1-4244-9472-9. DOI: 10.1109/ISCAS.2011.5938108
REIS, R. (2011B), “Power Consumption & Reliability in NanoCMOS”, IEEE NANO, 11th International Conference on Nanotechnology, Portland, USA, August 15-19, 2011 (invited talk), p.711-714. ISBN 978-1-4577-1515-0, DOI: 10.1109/NANO.2011.6144656
The Connectivist (2014), [link]
The Economist (2010), 6 de setembro de 2010.
SIA (2015), Semiconductor Industry Association, Rebooting the IT Revolution, disponível em [link]
IHSMARKIT (2018), IoT Trend Watch 2018, disponível em: [link]
Techinsights (2017), [link]
VAZQUEZ, J., CHAMPAC, V., ZIESEMER, A., REIS, R., TEIXEIRA, I., SANTOS, M. e TEIXEIRA, P. (2012), “Delay Sensing for Long-Term Variations and Defects Monitoring in Safety–Critical Applications”, IN: Analog Integrated Circuits and Signal Processing, Volume 70, Number 2, 249-263, February 2012, Springer, ISSN 0925-1030, DOI: 10.1007/s10470-011-9789-0.
VELAZCO, R , FOUILLAT, P, REIS, R. (2007), “Radiation Effects on Embedded Systems”, Springer, June 2007. ISBN 978-1-4020-5645-1
Yakun Sophia Shao (2016), “Design and Modeling of Specialized Architectures, PhD Thesis, Harvard”, May 2016. Available at: [link]
ZIESEMER, A., REIS, R. (2015), “Physical Design Automation of Transistors Network”, Microelectronics Engineering, V. 148, p. 122-128, December 2015, Elsevier B.V., ISSN: 0167-9317, DOI: 10.1016/j.mee.2015.10.018
ANANTECH (2014), [link]
CONCEIÇÃO, C., MOURA, G., PISONI, F., REIS, R. (2017), “A Cell Clustering Technique to Reduce Transistor Count”, 24th IEEE International Conference on Electronics, Circuits and Systems – ICECS2017, Batumi, Georgia, December 5 - 8, 2017, p. 186-189, DOI: 10.1109/ICECS.2017.8291996
GENNARO, R., ROSA, F., OLIVEIRA, A., KASTENSMIDT, F., OST, L., REIS, R. (2017), “Analyzing the Impact of Fault Tolerance Methods in ARM Processors under Soft Errors Running Linux and Parallelization APIs”, IEEE Transactions on Nuclear Science, Volume: 64, Issue: 8, August 2017, ISSN: 1558-1578, DOI: 10.1109/TNS.2017.2706519
LAZZARI, C., WIRTH, G., KASTENSMIDT, F., ANGHEL, L., REIS, R. (2011), “Asymmetric Transistor Sizing Targeting Radiation-Hardened Circuits”, Journal on Electrical Engineering, Springer, DOI: 10.1007/s00202-011-0212-8, June 2011.
KASTENSMIDT, F., CARRO, L.; REIS, R. (2006), “Fault-Tolerance Techniques for SRAM-Based FPGA”, Springer. April 2006, 183 p., ISBN 0-387-31068-1
NEUBERGER, G., WIRTH, G., REIS, R., (2014) “Protecting Chips Against Hold Time Violations Due to Variability”, Springer, 107 p., 2014. ISBN 978-94-007-2426-6. DOI: 10.1007/978-94-007-2427-3
NICOLAIDIS, M. (1999), “Time redundancy based soft-error tolerance to rescue nanometer technologies”. In: IEEE VLSI TEST SYMPOSIUM, 17., 1999. Proceedings... IEEE Computer Society, 1999. p. 86-94.
POSSER, G., FLACH, G., WILKE, G., REIS, R. (2011), “Gate Sizing Minimizing Delay and Area”, ISVLSI2011. IEEE Computer Society Annual Symposium on VLSI, Chennai, India, July 4-6, 2011. p. 315-316, ISBN 978-0-7695-4447-2. DOI: 10.1109/ISVLSI.2011.92
REIMANN, T., SZE, C., REIS, R. (2016), “Challenges of Cell Selection Algorithms in Industrial High Performance Microprocessor Designs”, Integration, Elsevier B. V., Volume 52, January 2016, Pages 347-354, ISSN: 0167-9260, DOI: 10.1016/j.vlsi.2015.09.001
REIS, R., (2010) “Redução de Consumo pela Otimização de Componentes”, SEMISH 2010, Anais do 37º Seminário Integrado de Software e Hardware, Belo Horizonte, 21 a 22 de julho de 2010, p. 371-379, ISSN: 2175-2761.
REIS, R. (2011A), “Design Automation of Transistor Networks, a New Challenge”. IEEE International Symposium on Circuits and Systems, ISCAS2011, Rio de Janeiro, Brasil, May 15-19, 2011. IEEE Press. p. 2485-2488, ISBN: 978-1-4244-9472-9. DOI: 10.1109/ISCAS.2011.5938108
REIS, R. (2011B), “Power Consumption & Reliability in NanoCMOS”, IEEE NANO, 11th International Conference on Nanotechnology, Portland, USA, August 15-19, 2011 (invited talk), p.711-714. ISBN 978-1-4577-1515-0, DOI: 10.1109/NANO.2011.6144656
The Connectivist (2014), [link]
The Economist (2010), 6 de setembro de 2010.
SIA (2015), Semiconductor Industry Association, Rebooting the IT Revolution, disponível em [link]
IHSMARKIT (2018), IoT Trend Watch 2018, disponível em: [link]
Techinsights (2017), [link]
VAZQUEZ, J., CHAMPAC, V., ZIESEMER, A., REIS, R., TEIXEIRA, I., SANTOS, M. e TEIXEIRA, P. (2012), “Delay Sensing for Long-Term Variations and Defects Monitoring in Safety–Critical Applications”, IN: Analog Integrated Circuits and Signal Processing, Volume 70, Number 2, 249-263, February 2012, Springer, ISSN 0925-1030, DOI: 10.1007/s10470-011-9789-0.
VELAZCO, R , FOUILLAT, P, REIS, R. (2007), “Radiation Effects on Embedded Systems”, Springer, June 2007. ISBN 978-1-4020-5645-1
Yakun Sophia Shao (2016), “Design and Modeling of Specialized Architectures, PhD Thesis, Harvard”, May 2016. Available at: [link]
ZIESEMER, A., REIS, R. (2015), “Physical Design Automation of Transistors Network”, Microelectronics Engineering, V. 148, p. 122-128, December 2015, Elsevier B.V., ISSN: 0167-9317, DOI: 10.1016/j.mee.2015.10.018
Publicado
26/07/2018
Como Citar
REIS, Ricardo.
Estratégias para a Redução de Consumo de Energia e Aumento de Confiabilidade em IoT. In: SEMINÁRIO INTEGRADO DE SOFTWARE E HARDWARE (SEMISH), 45. , 2018, Natal.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2018
.
p. 36-47.
ISSN 2595-6205.
DOI: https://doi.org/10.5753/semish.2018.3430.
