A Hardware Architecture for Smoothing Filters in H.266/VVC Intra-Prediction

• Sara Vitória Henssler UNIPAMPA
• Luciano Volcan Agostini UFPel
• Marcel Moscarelli Corrêa IFSul

DOI: https://doi.org/10.5753/webmedia.2025.15379

Resumo

This paper presents a hardware architecture for the preprocessing smoothing filters used in the intra prediction module of the H.266 Versatile Video Coding (H.266/VVC) standard, applicable to both the encoder and decoder sides. The design was fully described in VHDL and synthesized to an Intel Cyclone V FPGA, utilizing 6,961 adaptive logic modules and 4,158 registers, demonstrating feasibility for FPGA implementation with room for integration with a larger intra prediction module. Operating at a maximum frequency of 96.3 MHz without pipelining, the architecture achieves a decoding throughput of up to 2,972 frames per second (fps) for the 1080p resolution, 743 fps for UHD 4K, and 185 fps for UHD 8K, showing that a much lower clock operation can be used for real-time performance. For encoding, the throughput was estimated by targeting a 60 fps rate at 1080p resolution, resulting in an upper bound of approximately 3,171 CUs evaluated per CTU, compatible with fast decision algorithms used in practical encoders.

Palavras-chave: hardware, intra prediction, video coding, h.266, vvc

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