3D Graphic Simulation Environment for Teaching Processor Architecture

• Eduardo de Lucena Falcão UFPB
• Erick Vagner Cabral de Lima Borges UFPB
• Igor Lucena Peixoto Andrezza UFPB
• Glauco Sousa e Silva UFPB
• Kívio Grangeiro Wanderley UFPB
• Berg Élisson Sampaio Cavalcante UFPB
• Hamilton Soares da Silva UFPB

Abstract

In Computer Architecture, one of the challenges is getting the students to understand the workings of a processor correctly. To assist in this task, applications are used to simulate these architectures. From these barriers of education, is proposed the development of an application that visually simulates the instructions of an implementable and didactic architecture. Such instructions can be visualized, both with and without pipeline, which facilitates the comprehension of this concept, and of the operation of a processor while executing an instruction.

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