Avaliação do Consumo Energético em Arquiteturas Multi-Core com Memória Cache Compartilhada

• Matheus Souza PUC Minas
• Henrique Freitas PUC Minas
• Marco Alves UFRGS
• Philippe Navaux UFRGS

Abstract

A design challenge for multi-core processors is to obtain the best possible level of energy efficiency. This paper presents results concerning the energy consumption of a simulated chip-multiprocessor architecture (CMP) with different shared L2 cache models under different multi-threaded workloads. The decrease in cache size and its distribution in groups of processing cores made possible an overall reduction in power consumption up to 18.10%, and 70.51% at the memory access, with decrease in performance up to 57.13% and increase in L2 cache misses up to 93.66%. In general, the version with 32 L2 private cache banks consumed up to 53.27% less energy.

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