Projeto e Implementação de Decodificadores de Código em Plataformas FPGA

• Felipe de Oliveira de Araújo UFMS
• Ricardo Ribeiro dos Santos UFMS

Abstract

This paper presents the design, implementation, and characterization of instruction decoders on an ILP (Instruction-Level Parallelism) processor named ρ-VEX. The design and implementation of the instruction decoder is based on the Pattern Based Instruction Word (PBIW) encoding technique. PBIW is an instruction encoding technique independent of the instruction set. The design and implementation of the PBIW instruction decoder enable to evaluate the impacts of the decoding technique on the processor hardware. Specifically, the experiments and results show alternatives for minimizing the power consumption and area of the processor.

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