Stitching FPGA Dies into a Unified Pipeline for Seismic Stencil Acceleration

• Lucas R. Cilento USP
• Edson S. Gomi USP

DOI: https://doi.org/10.5753/eradsp.2026.30776

Resumo

Finite-difference solvers for the 3D acoustic wave equation are widely used in seismic imaging. We present a multi-die FPGA architecture that exploits the three dies of a Xilinx Alveo U55C as a single computational pipeline interconnected by on-chip AXI-Stream FIFOs. By streaming each tile across all dies in one pass, the design eliminates intermediate off-chip memory transfers and increases the effective stencil depth available to the computation. Experiments show approximately 1.8× less data movement than a conventional replicated design, increasing sustained performance from 96 to 175 GFLOP/s.

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