On the Use of Clonal Selection Principle in Cartesian Genetic Programming for Designing Combinational Logic Circuits
Evolutionary techniques have been used in the design and optimization of combinational logic circuits. This procedure is called evolvable hardware and Cartesian Genetic Programming (CGP) is the evolutionary technique with the best performance in this context. Despite the good results obtained by CGP techniques, its search procedure usually evolves a single candidate solution by an evolution strategy and this approach tends to be trapped in local optima. On the other hand, clonal selection techniques in general, and CLONALG in particular, were designed to avoid converging to a low-quality local optimum. Thus, we propose here using the representation of CGP with the search procedure of a Clonal Selection Algorithm to minimize the number of transistors of combinational logic circuits. Furthermore, a parameter sensitivity analysis is performed. The results are assessed considering a benchmark from the literature and showed a reduction in the number of transistors when compared to the baseline ESPRESSO.
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