Implementation of the SHA-3 family using AVX512 instructions
Resumo
AVX512 is the newest instruction set on the Skylake-X that extends the number of registers and provides simultaneous execution of operations over register vectors of 512 bits. This work presents how the AVX512 instruction set can be exploited to develop a fast software implementation of the Secure Hash Algorithm-3 (SHA-3) family. We achieved a speedup of around 30% when compared with x64 and AVX2 implementations. We also present a parallel implementation of two eXtendable-Output Functions (XOFs), called SHAKE128 and SHAKE256, using AVX512 that are about 5.22× faster than a single message implementation. The SHAKE functions can be used to speedup hash-based digital signatures.
Referências
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Huelsing, A., Butin, D., Gazdag, S., Rijneveld, J., and Mohaisen, A. (2018). Xmss: extended merkle signature scheme. Technical report.
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Merkle, R. (1990). A certified digital signature. In Brassard, G., editor, Advances in Cryptology — CRYPTO’ 89 Proceedings, volume 435 of Lecture Notes in Computer Science, pages 218–238. Springer New York.
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Wang, X., Yin, Y. L., and Yu, H. (2005). Finding collisions in the full sha-1. In Advances in Cryptology–CRYPTO 2005, pages 17–36. Springer.
Bernstein, D. J. and Lange, T. (2018). ebacs: Ecrypt benchmarking of cryptographic systems.
Bertoni, G., Daemen, J., Peeters, M., and Assche, G. (2009). Keccak specifications. Version 2 (as updated for round 2).
Bertoni, G., Daemen, J., Peeters, M., and Van Assche, G. (2007). Sponge functions. In ECRYPT hash workshop, volume 2007.
Cooperation, I. (2016). Intel architecture instruction set extensions programming reference. Intel Corp., Mountain View, CA, USA, Tech. Rep, pages 319433–030.
Corporation, I. (2008). Intel R© Pentium processor with MMXTM technology documentation. [link].
Corporation, I. (2009). Define SSE2, SSE3 and SSE4. [link].
Corporation, I. (2011). Intel R© Advanced Vector Extensions Programming Reference. [link].
FIPS, P. (2014). Secure hash algorithm-3 (sha-3) standard: Permutation-based hash and extendable-output functions. National Institute for Standards and Technology (NIST), 202(0).
Fog, A. (2018a). Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs.
Fog, A. (2018b). The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers.
Huelsing, A., Butin, D., Gazdag, S., Rijneveld, J., and Mohaisen, A. (2018). Xmss: extended merkle signature scheme. Technical report.
Indesteege, S., Mendel, F., Preneel, B., and Rechberger, C. (2009). Collisions and other non-random properties for step-reduced sha-256. In Selected Areas in Cryptography, pages 276–293. Springer.
Merkle, R. (1990). A certified digital signature. In Brassard, G., editor, Advances in Cryptology — CRYPTO’ 89 Proceedings, volume 435 of Lecture Notes in Computer Science, pages 218–238. Springer New York.
Stevens, M., Bursztein, E., Karpman, P., Albertini, A., and Markov, Y. (2017). The first collision for full sha-1. In Annual International Cryptology Conference, pages 570–596. Springer.
Wang, X., Yin, Y. L., and Yu, H. (2005). Finding collisions in the full sha-1. In Advances in Cryptology–CRYPTO 2005, pages 17–36. Springer.
Publicado
25/10/2018
Como Citar
CABRAL, Roberto; LÓPEZ, Julio.
Implementation of the SHA-3 family using AVX512 instructions. In: SIMPÓSIO BRASILEIRO DE SEGURANÇA DA INFORMAÇÃO E DE SISTEMAS COMPUTACIONAIS (SBSEG), 18. , 2018, Natal.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2018
.
p. 361-368.
DOI: https://doi.org/10.5753/sbseg.2018.4266.
