Implementation of 32-bit Multiplication Unit for a Out-of-Order RISC-V Processor utilizing Radix-4 Booth Algorithm and Wallace Tree

• Enzo E. C. Ibiapina UFPI
• Benjamin S. Silva UFPI
• Ivan S. Silva UFPI

DOI: https://doi.org/10.5753/ercemapi.2024.243779

Resumo

Multiplication is a fundamental arithmetic operation critical to a broad spectrum of computational applications. Its implementation in hardware significantly influences overall system performance, given that multiplication inherently involves a series of successive addition operations, which can introduce potential bottlenecks in pipelined systems. This paper focuses on the design and implementation of an efficient 32-bit multiplier unit for educational purposes, within the context of a superscalar out-of-order RISC-V architecture, by utilizing and presenting standard techniques used on the industry in order to achieve fast multiplication results.

Referências

Booth, A. D. (1951). A signed binary multiplication technique. The Quarterly Journal of Mechanics and Applied Mathematics, pages 236–240.

Edavoor, P. J., Raveendran, S., and Rahulkar, A. D. (2020). Approximate multiplier design using novel dual-stage 4:2 compressors. IEEE Access, 8:48337–48351.

Foundation, R.-V. (2019). RISC-V Instruction Set Manual Volume I: User-Level ISA. [link]. Online; accessed in: 12-July-2024.

Foundation, R.-V. (2024). About RISC-V. [link]. Online; accessed in: 12-July-2024.

Koren, I. (2002). Computer Arithmetic Algorithms. A K Peters/CRC Press, 2th edition.

OpenAI (2024). ChatGPT. [link]. Online; accessed in: 12-July-2024.

Wallace, C. S. (1964). A suggestion for a fast multiplier. IEEE Transactions on Electronic Computers, EC-13(1):14–17.

Yeh, W.-C. and Jen, C.-W. (2000). High-speed booth encoded parallel multiplier design. IEEE Transactions on Computers, 49(7):692–701.

Zhang, M., Nishizawa, S., and Kimura, S. (2023). Area efficient approximate 4–2 compressor and probability-based error adjustment for approximate multiplier. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(5):1714–1718.