Exploiting loop-level parallelism with the Shift Architecture

• C. D. Lima University of Tohoku
• T. Nakamura University of Tohoku

Resumo

The limited amount of instruction-level parallelism inherent in applications is a limiting factor for improving the performance of most conventional microprocessors. A promising solution to overcome this problem is to exploit coarser granularities of parallelism. In this paper, we propose exploiting loop-level parallelism in a multithreaded fashion. We use the Shift Architecture as a baseline architecture, with improved compiler support and register file. The compiler converts iterations of a loop into threads, to be executed by multiple processing elements. The hardware provides a selective register shifting mechanism in order to allow the execution of loops containing loop-carried data dependences, which are very difficult to execute by using conventional architectures. In this paper, we simulate and discuss the parameters of major importance for the implementation of this architectural approach. Our initial results show that, on two simple numerical benchmarks, a considerable amount of iteration overlapping can be potentially achieved by an implementation of the Shift Architecture, in comparison with a multiprocessor machine.

Palavras-chave: Parallel processing, Computer architecture, Microprocessors, Laboratories, Application software, Yarn, Hardware, Continuous improvement, Delay, Proposals